Morda za lažje razumevanje PLLja in XTAL oscilatorja v MC še konkreten primer za NXP ARM:
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up into the range of 10 MHz to 60 MHz with a Current Controlled
Oscillator (CCO). The multiplier can be an integer value from 1 to 32 (in practice, the
multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper
frequency limit of the CPU). The CCO operates in the range of 156 MHz to 320 MHz, so
there is an additional divider in the loop to keep the CCO within its frequency range while
the PLL is providing the desired output frequency. The output divider may be set to divide
by 2, 4, 8, or 16 to produce the output clock. Since the minimum output divider value is 2,
it is insured that the PLL output has a 50 % duty cycle.
Torej:
- referenčni vhod od 10MHz do 25MHz,
- VCO (CCO) od 156MHz do 320MHz,
- izhod takta za MCU 10MHz do 60MHz.
LP, Bojan